A Streamlined Architecture For 3-D Discrete Wavelet Transformation And Inverse Discrete Wavelet Transform

This paper presents an architecture of the lifting based running 3-D discrete wavelet transform (DWT), which is a powerful image and video compression algorithm. The proposed design is one of the first lifting based complete 3DDWT architectures without group of pictures restriction. The new computing technique based on analysis of lifting signal flow graph minimizes the storage requirement. This architecture enjoys reduced memory referencing and related low power consumption, low latency, and high throughput compared to those of earlier reported works. Further, the digital data can be retrieved using Inverse Discrete Wavelet Transform (IDWT). The images need to be retrieved without loosing of information. The proposed architecture has been successfully implemented on Xilinx Spartan series field-programmable gate array, offering a speed of 40 MHz, making it suitable for realtime compression even with large frame dimensions. Moreover, the architecture is fully scalable beyond the present coherent Daubechies filterbank (9, 7).